This application claims the priority of Korean Patent Application No. 2003-57512, filed on Aug. 20, 2003, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a repair apparatus and method for a semiconductor memory device.
2. Description of the Related Art
As semiconductor memory devices become more and more highly integrated, a process by which they are manufactured also becomes complicated. Consequently, the number of memory cells that fail due to damage during the manufacturing process increases. For this reason, most semiconductor memory devices are designed to include a small number of redundancy memory cell arrays that repair defective cells of a main memory cell array. A conventional repair apparatus for a semiconductor memory device which include such redundancy memory cell arrays is disclosed in U.S. Pat. No. 5,576,999.
A row line or a column line of a main memory cell array including at least one defective cell may be replaced with redundancy memory cells. For the replacement, the addresses of defective cells are required to be programmed in a repair control circuit of a repair apparatus before the replacement. The repair control circuit programs the addresses of the defective cells by selectively cutting fuses included in the repair control circuit. In general, the fuses are laser fuses that can be cut using a laser beam or electrical fuses that can be cut electrically.
FIG. 1 is a block diagram of a semiconductor memory device 100 including a conventional repair apparatus 150. Some internal circuits in the semiconductor memory device 100 are not illustrated in FIG. 1 for convenience. Referring to FIG. 1, the semiconductor memory device 100 includes a main memory cell array 110, a normal row decoder 120, a row address buffer 130, a row predecoder 140, and the repair apparatus 150.
The repair apparatus 150 includes a first redundancy memory cell array 151, a second redundancy memory cell array 152, a first redundancy row decoder 153, a second redundancy row decoder 154, and a repair control circuit 155. The repair control circuit 155 includes a first comparator 161, a second comparator 162, and a fuse box 163.
The first redundancy memory cell array 151, the first redundancy row decoder 153, and the first comparator 161 repair a defective cell, i.e., a first defective cell, in the main memory cell array 110 which is detected during a wafer-level test process. The second redundancy memory cell array 152, the second redundancy row decoder 154, the second comparator 162, and the fuse box 163 repair a defective cell, i.e., a second defective cell, in the main memory cell array 110 which is defected during a test, i.e., post package test, following a packaging process.
The first comparator 161 includes a plurality of fuses F1 through F24, of FIG. 2, which are programmed with the address of the first defective cell. The first comparator 161 will be described in a greater detail with reference to FIG. 2. The fuse box 163 is programmed with the address of the second defective cell.
Referring to FIG. 2, the first comparator 161 includes an address comparing circuit 91 and a logic circuit 92. The address comparing circuit 91 includes a plurality of transistors 21 through 49 and a plurality of fuses F1 through F24.
The elements of the conventional repair apparatus 150 are divided into two groups according to their functions. The elements belonging to one group are the first redundancy memory cell array 151, the first redundancy row decoder 153, and the first comparator 161. These elements repair a defective cell detected during a wafer-level test. The elements belonging to the other group are the second redundancy memory cell array 152, the second redundancy row decoder 154, the second comparator 162, and the fuse box 163. These repair a defective cell detected during a post package test. Also, the repair apparatus 150 includes the first and second redundancy memory cell arrays 151 and 152 that are used by the above two groups, respectively. The first and second redundancy memory cell arrays 151 and 152 are separated from each other, and the number of their redundancy memory cells is limited to minimize space occupied by the first and second redundancy memory cell arrays 151 and 152 in the semiconductor memory device 100.
Accordingly, the conventional repair apparatus 150 is disadvantageous in a total number of memory cells for repairing defective cells detected during the wafer-level and post package tests. Also, since signal paths of the two groups of elements are different from each other, timing control must be individually performed on the two groups of elements.